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Electronic design automation
Results: 1598

#	Item
731	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 3, JUNE[removed]Transactions Briefs__________________________________________________________________ Board-Level Multiterminal Net Assignm Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2003-07-31 11:09:07 Logic in computer science NP-complete problems Electronic design automation Formal methods Boolean algebra Boolean satisfiability problem Field-programmable gate array MOS Technology SID Hardware emulation Theoretical computer science Electronic engineering Applied mathematics
732	Global Delay Optimization using Structural Choices Abstract This paper presents a fast global method for delay optimization after technology mapping. Timing analysis is used to identify timing-critical areas in the mappe Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-09-11 21:52:58 Digital electronics Electrical circuits Diagrams And-inverter graph Field-programmable gate array Static timing analysis Propagation delay Logic synthesis Retiming Electronic engineering Electronic design automation Formal methods
733	社団法人電子情報通信学会 THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS 信学技報 TECHNICAL REPORT OF IEICE Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2002-11-23 21:54:00 Computing Diagrams Binary decision diagram Model checking Electronic design automation Lookup table Boolean function Field-programmable gate array Canonical form Mathematics Boolean algebra Electronic engineering
734	Incremental Sequential Equivalence Checking and Subgraph Isomorphism Sayak Ray Alan Mishchenko Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2009-07-12 14:37:50 Applied mathematics And-inverter graph Electronic design automation Subgraph isomorphism problem Automatic test pattern generation Graph isomorphism Theoretical computer science Mathematics Diagrams
735	Technology Mapping with Boolean Matching, Supergates and Choices Alan Mishchenko Satrajit Chatterjee Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-04-19 22:57:46 Logic synthesis Circuit Standard cell Boolean function Electronic engineering Electronic design automation And-inverter graph
736	VLSI DESIGN 1996, Vol. 4, No. 2, pp. i-ii (C[removed]Reprints available directly from the publisher Add to Reading List Source URL: downloads.hindawi.com Language: English - Date: 2014-05-11 09:05:38 Logic design Field-programmable gate array Hindawi Publishing Corporation CPU design Logic simulation Parallel computing Application-specific integrated circuit Digital electronics Simulation Electronic engineering Electronic design automation Integrated circuits
737	Scalably-Verifiable Sequential Synthesis Robert Brayton Alan Mishchenko Department of EECS, University of California, Berkeley Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2007-10-02 14:31:33 Electronic design automation Digital electronics Logic in computer science Electrical circuits And-inverter graph Retiming Automatic test pattern generation Formal verification Combinational logic Electronic engineering Formal methods Theoretical computer science
738	Web-based Metaprogrammable Frontend for Molecular Dynamics Simulations Gergely Varga1, Sara Toth1, Christopher R. Iacovella2, Janos Sallai1, Peter Volgyesi1, Akos Ledeczi1 and Peter T. Cummings2 1 Add to Reading List Source URL: www.isis.vanderbilt.edu Language: English - Date: 2013-07-30 14:40:26 Science Simulation software Operations research Simulation NanoHUB Network simulation Molecular dynamics Computer simulation Deterministic simulation Computing Electronic engineering Electronic design automation
739	Reasoning about A c t i o n in Polynomial T i m e T h o m a s D r a k e n g r e n and M a r c u s B j a r e l a n d Department of Computer and Information Science Link6ping University, S[removed]Linkoping, Sweden email: { Add to Reading List Source URL: www.ida.liu.se Language: English - Date: 2012-01-24 05:33:24 Logic in computer science Boolean algebra Boolean satisfiability problem Electronic design automation P-complete Temporal logic Frame problem Cook–Levin theorem Theoretical computer science Applied mathematics Mathematics
740	Pluto Manager A programming tool for your safety functions Pluto Manager is a software tailored for the Pluto Safety PLC. Programming is done in ladder, and together with the function block, creates the structure of you Add to Reading List Source URL: www.jokabsafetyna.com Language: English - Date: 2013-07-18 16:50:24 Function Embedded systems Mathematics Electronic design automation Ladder logic

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